Microprocessor-accessible memory devices have traditionally been classified as either non-volatile or volatile memory devices. Non-volatile memory devices are capable of retaining stored information even when power to the memory device is turned off. However, non-volatile memory devices occupy a large amount of space and consume large quantities of power, making these devices unsuitable for use in portable devices or as substitutes for frequently-accessed volatile memory devices. On the other hand, volatile memory devices tend to provide greater storage capability and programming options than non-volatile memory devices. Volatile memory devices also generally consume less power than non-volatile devices. However, volatile memory devices require a continuous power supply in order to retain stored memory content.
Commercially viable memory devices that are randomly accessed, have relatively low power consumption, and are semi-volatile or non-volatile are desired. Various implementations of such semi-volatile and nonvolatile random access memory devices are being developed. These devices store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages which in turn changes cell resistance. Examples of variable resistance memory devices being investigated include memories using variable resistance polymers, perovskite, doped amorphous silicon, phase-changing glasses, or doped chalcogenide glass, among others.
In a variable resistance memory cell, a first value may be written to the variable resistance memory cell by applying a current generated by a predetermined voltage level. The applied current changes the electrical resistance across the memory cell. A second value, or the default value, may be written or restored in the memory cell by applying a current due to a second voltage, thereby changing the resistance across the memory cell to the original resistance level. Each resistance state is stable, so that the memory cells are capable of retaining their stored values without being frequently refreshed. The variable resistance materials can thus be “programmed” to any of the stable resistance values.
FIG. 1 shows a basic composition of a variable resistance memory cell 10 constructed over a substrate 12, having a variable resistance material 16 formed between two electrodes 14, 18. One type of variable resistance material may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type of variable resistance material may include perovskite materials such as Pr(1−x)CaxMnO3 (PCMO), La(1−x)CaxMnO3 (LCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO) as disclosed in U.S. Pat. No. 6,473,332 to Ignatiev et al. Still another type of variable resistance material may be a doped chalcogenide glass of the formula AxBy, where “B” is selected from among S, Se and Te and mixtures thereof, and where “A” includes at least one element from Group IIIA (B, Al, Ga, In, Tl), Group IVA (C, Si, Ge, Sn, Pb), Group VA (N, P, As, Sb, Bi), or Group VIIA (F, Cl, Br, I, At) of the periodic table, and with the dopant being selected from among the noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed in U.S. Published Application Nos. 2003/0045054 and 2003/0047765 to Campbell et al. and Campbell, respectively. Yet another type of variable resistance material includes a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, such as that disclosed in U.S. Pat. No. 6,072,716 to Jacobson et al. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
While the overall operating scheme of the memory cell 10 may be similar regardless of the type of variable resistance material 16 used, much research has focused on memory devices using memory elements having doped chalcogenide materials as the variable resistance material. More specifically, memory cells having a variable resistance material formed of germanium-selenide glass having a stoichiometry of GexSe(100−x), with x ranging from about 20 to about 43, which are doped with metal ions, have been shown to be particularly promising for providing a viable commercial alternative to traditional non-volatile random-access memory devices.
In FIG. 2, a typical prior art ionic chalcogenide glass variable resistance memory cell 100 is shown and includes an access device 102, a chalcogenide variable resistance memory element 104, and a common cell plate 110. The access device 102 is a transistor having a gate 102a coupled to a word line 106 and one terminal (source) 102b coupled to a bit line 108. The other terminal (drain) 102c of the access device 102 is coupled to one end of the chalcogenide variable resistance memory element 104, while the other end of the chalcogenide variable resistance memory element 104 is coupled to the cell plate 110. The cell plate 110 may span and be coupled to several other chalcogenide variable resistance memory cells, and may form the anode of all the memory elements 104 in an array of chalcogenide variable resistance memory cells. The cell plate 110 is also coupled to a potential source 112.
Application of the write and erase voltages depends on the type of chalcogenide variable resistance memory cells. In ionic chalcogenide variable resistance memory cells, application of the write voltage may be achieved by raising the potential at the cell plate 110 (anode) relative to the access device drain 102b by applying or raising the voltage at the potential source 112, lowering the potential of the bit line 108, or a combination of both. To erase a programmed memory element 104, a negative voltage having a magnitude of at least a threshold erase voltage is applied between the anode and the cathode of the memory element 104, such that the potential at the cell plate 110 is lower than the potential of the bit line 108. In a read operation, the resistance of the memory element 104 is measured between the cell plate 110 and the readout line 120.
In phase change chalcogenide variable resistance memory cells, an erase voltage may be applied by creating a brief but sufficient voltage potential across memory element 104. The voltage potential may be in either direction and is caused by changing the potential at the potential source 112, the bit line 108, or a combination of both. The erase voltage is strong enough to generate a current through the memory element 104 that melts the phase change material in the memory element 104. When the erase voltage is abruptly turned off, the phase change material in memory element 104 cools into an amorphous, non-crystalline state with high resistance. A write current is applied by application of a lesser but more sustained write voltage across memory element 104. The applied write current need not be in a specific direction, but must be sufficient to “warm” the phase change material in the memory element 104 to allow rearrangement of the phase change material into a low-resistance crystalline state. As with the ionic chalcogenide variable resistance memory cells, the resistance of the memory element 104 is measured between the cell plate 110 and the readout line 120.
Chalcogenide variable resistance memory cells are arranged as an array of memory cells and are written, erased, and read using a controller. FIG. 3 illustrates a prior art memory device 200 comprising an array of memory cells 100a-100f arranged in rows and columns. The memory cells 100a-100f along any given bit line 108a, 108b do not share a common word line 106a-106c. Conversely, the memory cells 100a-100f along any given word line 106a-106c do not share a common bit line 108a-108b. In this manner, each memory cell is uniquely identified by the combined selection of the word line to which the gate of the memory cell access device is connected, and the bit line to which the source of the memory cell access device is connected.
Each word line 106a-106c is connected to a word line driver 202a-202c via a respective transistor 204a-204c for selecting the respective word line for an access operation. The gates of the transistors 204a-204c are used to selectively couple or decouple the word lines 106a-106c to or from the word line drivers 202a-202c. Similarly, each bit line 108a, 108b is coupled to a driver 206a, 206b via selector gates 208a, 208b. The current and/or resistance of a selected memory cell 100a-100f is measured by sense amplifiers 210a, 210b connected respectively to the bit lines 108a, 108b. 
For simplicity, FIG. 3 illustrates a memory array having only two rows of memory cells 100 on two bit lines 108a-108b and three columns of memory cells 100 on three word lines 106a-106c. However, it should be understood that in practical applications, memory devices would have significantly more cells in an array. For example, an actual memory device may include several million memory cells 100 arranged in a number of subarrays.
Generally, a chalcogenide variable resistance memory cell has an initial “off” state resistance of over 100 kΩ (for example, 1 MΩ). To perform a write operation on a chalcogenide memory cell in its normal high resistive state, a sufficiently strong write current must be applied. Upon applying the threshold level or write voltage, the resistance across the memory cell changes to a level dramatically reduced from the resistance in its normal state. The new resistance of the memory cell is less than 100 kΩ (for example, 20 kΩ). The cell is considered to be in the “on” state while in the low-resistive state.
The chalcogenide variable resistance memory cell retains this new lower level of resistivity until the resistivity is changed by another qualifying voltage level applied to one of the electrodes of the cell. For example, in an ionic chalcogenide variable resistance memory cell, the memory cell is returned to the high resistance state by applying an erase voltage thereto in the negative direction of the voltage applied in the write operation (to achieve the lower resistance state), thus inducing an erase current to flow through the memory cell in a direction opposite that of the applied write current. The erase voltage may or may not be the same magnitude as the write voltage.
Over time, however, the resistance level resulting from application of various write and erase currents to a chalcogenide variable resistance memory cell tend to drift. Resistance drift occurs in various types of chalcogenide variable resistance memory cells, including both phase change and ionic chalcogenide variable resistance memory cells.
In a phase change chalcogenide variable resistance memory cell, write and erase currents are applied that actually melt or warm the chalcogenide variable resistance memory cell. The write and erase currents are generated by applying a specific voltage potential to the chalcogenide variable resistance memory cell. The generated current, then, is a function of both the applied voltage and the resistance of the chalcogenide variable resistance memory cell (I=V/R). However, over time and repeated phase changes, the volume of cell material that actually changes phase (and hence resistance) actually decreases. The result is an overall increase in the resistance of the chalcogenide variable resistance memory cell. Thus, for a given applied voltage potential, less current is generated. At some point, the current generated may be insufficient to adequately melt or warm the memory cell.
In the case of ionic chalcogenide variable resistance memory cells, resistance drift may be demonstrated using voltage/resistance curves for write and erase operations. A standard voltage/resistance curve for a write operation performed on a properly functioning ionic chalcogenide variable resistance memory cell is illustrated in FIG. 4. A voltage/resistance curve, such as that shown in FIG. 4, is derived by measuring the resistance across the ionic chalcogenide variable resistance memory cell as a function of voltage for a given current. The initial or normal resistance level of an ionic chalcogenide variable resistance memory cell is shown as ROFF, which is above a minimum threshold level REMin in which the ionic chalcogenide variable resistance memory cell is stable in a high resistance state. When the ionic chalcogenide variable resistance memory cell is in the high resistance state and VTW is applied to the cell, the resistance drops to the level indicated by RON, which is below a maximum threshold level RWMax in which the ionic chalcogenide variable resistance memory cell is stable in a low resistance state.
However, the phenomenon of resistance drift in ionic chalcogenide variable resistance memory cells may eventually result in a memory cell being erased into an “off” state in which the resistance is unacceptably high. This can happen in as few as about 400 write and erase cycles. Typical life expectancies for random access memory devices are on the order of 1014 write/erase cycles. Thus, the resistance drift must be compensated for in order to improve the longevity of operation of the memory cell.
FIG. 5 depicts the case when the ionic chalcogenide variable resistance memory cell drifts towards a high resistance “off” state RDE, meaning that after repeated cycles over time, the “off” state resistance achieved upon application of a fixed erase voltage settles above the level ROFF shown in FIG. 4. Note that as RDE increases, the threshold write voltage VTW also increases. If VTW becomes larger than the applied write voltage, application of the write voltage will be insufficient to bring the memory cell to the maximum stable low resistance level RWMax. Once this condition is reached, subsequent write operations will fail to write the stored value in the ionic chalcogenide variable resistance memory cell, causing a breakdown in the function of the ionic chalcogenide variable resistance memory device. Additionally, continued erase cycles applied to these already high resistance state memory cells result in pushing the memory cells into an even higher resistance state.
One solution to the resistance drift problem described above in the context of both phase change and ionic chalcogenide variable resistance memory cells is to apply a higher write voltage, thereby inducing a stronger write current. A sufficiently strong write current could overcome the high resistance state, and successfully convert the chalcogenide variable resistance memory device into an “on” state. An alternative approach for the ionic chalcogenide variable resistance memory cell is to apply a sufficiently strong reset voltage to periodically correct the resistance drift and reset the on and off resistance levels. Unfortunately, the current drivers that are being used to provide the necessary higher write currents or reset currents are large; thus, unavoidably resulting in very large chalcogenide variable resistance memory devices and a low cell density.
There is, therefore, a desire and need to provide a controlled, high write current through a variable resistance memory device, for example, a chalcogenide variable resistance memory device in such a way as to overcome the increased resistance resulting from resistance creep, reduce the size of the variable resistance memory device and increase cell density.